4-bit array multiplier, RTL to GDSII

Krish Pandya and Vignesh Vembar, on the SkyWater SKY130 process. Every simulation on this page runs in your browser on our real netlists.

Report (PDF) and source code on GitHub.

Netlist
Corner, transistors and wires
Clock period

1. What does it compute?

a
b

Blue wires carry a 1. Play lights each wire when it settles, one full adder per step, so the carry crawls right to left.

2. How is the layout built?

Our final layout, built step by step from the snapshots of the LibreLane run.

    3. When does it break?

    Worst case for each new input over all 256 old ones. Click a square to watch it.

    Minimum clock period at each corner. Simulated is the slowest real transition. STA is LibreLane's sign-off bound minus its 0.25 ns clock uncertainty, and the simulated value stays below it.

    4. What happens inside one transition?

    5. Cycle by cycle